The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs, the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal or by enlarging or constricting the conducting channel and thereby controlling the current flowing between the source and the drain.
FIG. 1A illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor.
The space between the two diffusion areas is called the “channel”. The channel is where current flows, between the source (S) and the drain (D). A schematic symbol for an n-channel MOSFET appears to the left of FIG. 1A.
A thin dielectric layer is disposed on the substrate above the channel, and a “gate” structure (G) is disposed over the dielectric layer, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.)
Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded or biased at a desired voltage depending on applications.
Generally, when there is no voltage applied to the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity, plus or minus) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors are used, often paired with one another.
While particular n- and p-type dopants are described herein according to NMOS technology, it is to be appreciated that one or more aspects of the present invention are equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type dopants).
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching.
U.S. Pat. No. 3,387,286 (IBM; 1968) discloses field effect transistor memory. The memory is formed of an array of memory cells controlled for reading and writing by word lines and bit lines which are connected to the cells. Each cell is formed using a single FET and a single capacitor. The gate electrode of the FET is connected to the word line, the source terminal is connected to the bitline, and the drain terminal is connected to one of the (two) electrodes of the capacitor. The other electrode of the capacitor is connected to a reference potential. Information is stored by charging the capacitor through the transistor, and information is read out by discharging the capacitor through the transistor. During a “write” operation, the wordline which is connected to the gate of the transistor is energized to render the transistor conductive between source and drain. If a “zero” is to be stored, the bitline is not energized and the capacitor is not charged. If a “one” is to be stored, the bitline is energized and the capacitor is charged to substantially the potential (voltage) of the bitline signal. During “read” operations, only the wordline is energized and a signal is transmitted to the bit lie if a “one” has been stored previously (the capacitor is charged). Since the charge on the capacitor leaks off, it is necessary to periodically regenerate the information stored in the memory.
Memory Array Architecture Generally
Dynamic random access memory (DRAM) is a type of random access memory that usually stores data as electrical charges in a capacitor structure associated with a transistor. Since capacitors leak charge (generally, a capacitor is only useful for temporarily storing an electrical charge), the information (data) eventually fades unless the capacitor charge is refreshed (read, and re-written) periodically, such as every 64 ms (milliseconds). DRAM is usually arranged in an array of one capacitor and transistor per “cell”.
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
FIG. 1B illustrates an array of DRAM cells (labeled “a” through “i”) connected to a number of word lines (WL) and bit lines (BL). (Each DRAM cell is shown as comprising a FET and a capacitor.) For example, in the memory cell “e”, the FET has its gate connected to WL(n), its source is connected to BL(n), and its drain connected to one terminal of a capacitor. The other terminal of the capacitor is connected to ground. The nine memory cells (“a” through “i”) illustrated in FIG. 1B are exemplary of many millions of memory cells that may be resident on a single chip.
The gates of the FETs in memory cells “a”, “b” and “c” are all connected to the same word line WL(n−1), the gates of the FETs in memory cells “d”, “e” and “f” are all connected to the same word line WL(n), and the gates of the FETs in memory cells “g”, “h” and “i” are all connected to the same word line WL(n+1). Thus, a voltage applied to a given word line (WL) can affect many memory cells—namely all the memory cells connected to that word line.
Similarly, the sources of the FETs in memory cells “a”, “d” and “g” are all connected to the same bit line BL(n−1), the sources of the FETs in memory cells “b”, “e” and “h” are all connected to the same bit line BL(n), and the sources of the FETs in memory cells “c”, “f” and “i” are all connected to the same bit line BL(n+1). Thus, a voltage applied to a given bit line (BL) can affect many memory cells—namely all the memory cells connected to that word line.
DRAM (eDRAM)
Generally, the DRAM cells discussed herein comprise a capacitor formed in a deep trench (DT) in a substrate, and an “access transistor” formed on the surface of the substrate adjacent and atop the capacitor. The capacitor (“DT capacitor”) generally comprises a first conductive electrode called the “buried plate” which is a heavily doped region of the substrate surrounding the trench, a thin layer of insulating material such as oxide lining the trench, and a second conductive electrode such as a heavily doped polycrystalline plug (or “node”) disposed within the trench.
The transistor may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second electrode (node) of the capacitor.
In trench DRAM/eDRAM, the pass gate is desirably isolated from the underlying DT poly. In prior art the isolation is achieved by a thin shallow trench isolation (STI) oxide. However, thin STI oxide may be consumed before the pass gate is formed, leading to poor electrical isolation between the pass gate and DT poly. This is illustrated in FIGS. 2, 2A and 2B. In conventional memory arrays, the wordlines may serve as the gates of the cell (access) transistors.
FIG. 2 illustrates a DRAM cell 200 of the prior art, generally comprising an access transistor and an associated cell capacitor. Also shown is a wordline (WL), or “pass gate”, passing over the DT capacitor. The DRAM cell is generally formed, as follows.
Beginning with a semiconductor substrate 202, a deep trench (DT) 210 is formed, extending into the substrate 202, from a top (as viewed) surface thereof. The substrate 202 may comprise a SOI substrate having a layer 204 of silicon (SOI) on top of an insulating layer 206 which is atop an underlying silicon substrate 208. The insulating layer 206 typically comprises buried oxide (BOX). The deep trench (DT) 210 is for forming the cell capacitor (or “DT capacitor”), as follows. The trench 210 may have a width of about 50 nm to 200 nm and a depth of 1000 nm to 10000 nm, by way of example.
The cell capacitor generally comprises a first conductor called the “buried plate” which is a heavily doped region 212 of the substrate surrounding the trench 210, a thin layer 214 of insulating material lining the trench 210, and a second conductor 216 such as a heavily doped polycrystalline plug (or “node”, “DT poly”) disposed within the trench 210. A cell transistor (“access transistor”) 220 may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second conductor (node) of the capacitor, as follows.
The FET 220 comprises two spaced-apart diffusions, 222 and 224, within the surface of the substrate 202—one of which will serve as the “source” and the other of which will serve as the “drain” (D) of the transistor 220. The space between the two diffusion areas is called the “channel” (and is approximately where the legend “SOI” appears). A thin dielectric layer 226 is disposed on the substrate above the channel, and a “gate” structure (G) 228 is disposed over the dielectric layer 226, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) The gate 228 may be a portion of an elongate wordline, referred to (for this memory cell) as the “active wordline” (Active WL).
Generally, a plurality of DRAM/eDRAM memory cells in a given row of a memory array may utilize a given wordline as the gates for their access transistors. And the source diffusions of the DRAM/eDRAM memory cells in a given column of a memory array may utilize a given bitline as the sources (S) for their access transistors.
In modern CMOS technology, shallow trench isolation (STI) is commonly used to isolate one (or more) transistors from other transistors, for both logic and memory. As shown in FIG. 2, a shallow trench 232 may be formed, surrounding the access transistor 220 (only one side of the transistor is shown). Note that the trench 232 extends over the DT (node) poly 216, a top portion of which is adjacent the drain (D) of the transistor 220. Therefore, the trench 232 is less deep (thinner) over the DT poly 216 and immediately adjacent the drain (D) of the transistor 220, and may be deeper (thicker) further from the drain (D) of the transistor 220 (and, as shown, over top portion of the DT poly 216 which is distal from (not immediately adjacent to) the drain (D) of the transistor 220.
The STI trench 232 may be filled with an insulating material, such as oxide (STI oxide) 234. Because of the thin/thick trench geometry which has been described, the STI oxide will exhibit a thin portion 234a where it is proximal (adjacent to) the drain (D) of the transistor 220, and a thicker portion where it is distal from (not immediately adjacent to) the drain (D) of the transistor 220. Were the STI to be too thick immediately adjacent to the drain (D) of the transistor 220, this would interfere with the ohmic contact between the drain (D) and the node poly 216.
As mentioned above, a plurality of memory cells may be associated with a given word line (WL). Furthermore, the wordline may form the gates of the access transistors of those memory cells. In this example, the transistor 220 of the memory cell 200 is associated with the “active” wordline, which forms its gate (G). Another wordline, for another plurality of memory cells is shown, and is labelled “Pass WL” 240. And, as can be seen, the Pass WL 240 passes over the STI 234, above the node poly 216. This can create problems as follows.
The dashed-line circled area in FIG. 2 is expanded upon (magnified) in FIGS. 2A and 2B. FIG. 2A illustrates good isolation when thin STI oxide 234a remains over DT poly 216. FIG. 2B illustrates poor isolation when thin STI oxide (234a) is consumed over DT poly 216.
Related Patents and Publications
U.S. Pat. No. 6,998,666 (IBM; 2006), incorporated in it entirety by reference herein, discloses nitrided STI liner oxide for reduced corner device impact on vertical device performance. A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner. See also Publication No. 2005/0151181.
US Patent Publication No. 2006/0231918 (Popp et al.; 2006), incorporated in its entirety by reference herein, discloses field effect transistor and method for the production thereof. A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current ION can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.
U.S. Pat. No. 6,960,781 (Currie et al.; 2005), incorporated in its entirety by reference herein, discloses a shallow trench isolation process. A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.
U.S. Pat. No. 6,744,089 (Wu; 2004) incorporated in its entirety by reference herein, discloses a self-aligned lateral-transistor DRAM cell structure in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6 F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.
U.S. Pat. No. 6,509,226 (IBM; 2003), incorporated in its entirety by reference herein, discloses process for protecting array top oxide. Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack are deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An active area (AA) oxidation is performed, and the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.
Glossary
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the invention most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (®)
Anisotropicliterally, one directional. An example of an anisotropic process issunbathing. Only surfaces of the body exposed to (facing in thedirection of) the sun become tanned. See isotropic.bitThe word “bit” is a shortening of the words “binary digit.” A bitrefers to a digit in the binary numeral system (base 2). A given bit iseither a binary “1” or “0”. For example, the number 1001011 is 7bits long. The unit is sometimes abbreviated to “b”. Terms for largequantities of bits can be formed using the standard range of prefixes,such as kilobit (Kbit), megabit (Mbit) and gigabit (Gbit). A typicalunit of 8 bits is called a Byte.BLshort for bit line. The bit line is a conductor connected to at least oneof the source or drain terminals of a memory cell transistor. InDRAM, the bitline is typically connected to the source of thetransistor, and the drain is connected to one of the electrodes of thememory cell capacitor.CapacitorA capacitor is a two-terminal device (electrical or electroniccomponent) that can store energy in the electric field between a pairof conductive electrodes (called “plates”). The process of storingenergy in the capacitor is known as “charging”, and involves electriccharges of equal magnitude, but opposite polarity, building up oneach plate.Cell Well(CW) the cell well is an area in the silicon substrate that is preparedfor functioning as a transistor or memory cell device by doping withan electron acceptor material such as boron or indium (p, electronacceptors or holes) or with an electron donor material such asphosphorous or arsenic (n, electron donors). The depth of a cellwell is defined by the depth of the dopant distribution.CMOSshort for complementary metal oxide semiconductor. CMOSconsists of n-channel and p-channel MOS transistors. Due to verylow power consumption and dissipation as well as minimization ofthe current in “off” state, CMOS is a very effective deviceconfiguration for implementation of digital functions. CMOS is akey device in state-of-the-art silicon microelectronics.CMOS Inverter: A pair of two complementary transistors (ap-channel and an n-channel) with the source of the n-channeltransistor connected to the drain of the p-channel transistor, and thegates connected to each other. The output (drain of the p-channeltransistor) is high whenever the input (gate) is low and the other wayround. The CMOS inverter is the basic building block of CMOSdigital circuits.NMOS: n-channel CMOS.PMOS: p-channel CMOS.CMPshort for chemical-mechanical polishing. CMP is a process, usingboth chemicals and abrasives, comparable to lapping (analogous tosanding), for removing material from a built up structure. Forexample, after depositing and etching a number of elements, the topsurface of the resulting structure may very uneven, needing to besmoothed (or levelled) out, prior to performing a subsequentprocess step. Generally, CMP will level out the high spots, leavinga relatively smooth planar surface.CVDshort for chemical vapor deposition. CVD is a chemical processused to produce high-purity, high-performance solid materials. Theprocess is often used in the semiconductor industry to produce thinfilms. In a typical CVD process, the wafer (substrate) is exposed toone or more volatile precursors, which react and/or decompose onthe substrate surface to produce the desired deposit. CVD is used todeposit materials in various forms, including: monocrystalline,polycrystalline, amorphous, and epitaxial. These materials include:silicon, oxide, nitride and metals, such as are commonly used insemiconductor fabrication.depositionDeposition generally refers to the process of applying a materialover another material (or the substrate). Chemical vapor deposition(CVD) is a common technique for depositing materials. Other“deposition” techniques, such as for applying resist or glass, mayinclude “spin-on”, which generally involves providing a stream ofmaterial to the substrate, while the substrate is spinning, resulting ina relatively thin, flat, evenly-distributed coating of the material onthe underlying substrate.Dopantelement introduced into semiconductor to establish either p-type(acceptors) or n-type (donors) conductivity; common dopants insilicon: p-type, boron, B, Indium, In; n-type phosphorous, P,arsenic, As, antimony, Sb. Dopants are of two types - “donors” and“acceptors”. N type implants are donors and P type are acceptors.dopingdoping is the process of introducing impurities (dopants) into thesemiconductor substrate, or elements formed on the semiconductorsubstrate, and is often performed with a mask (or previously-formedelements in place) so that only certain areas of the substrate will bedoped. For example, doping is used to form the source and drainregions of an FET. An ion implanter is typically employed for theactual implantation. An inert carrier gas such as nitrogen is usuallyused to bring in the impurity source (dopant).Usually in doping, a dopant, a dosage and an energy levelare specified and/or a resulting doping level may be specified. Adosage may be specified in the number of atoms per cm2 and anenergy level (specified in keV, kilo-electron-volts), resulting in adoping level (concentration in the substrate) of a number of atomsper cm3. The number of atoms is commonly specified inexponential notation, where a number like “3E15” means 3 times 10to the 15th power, or a “3” followed by 15 zeroes(3,000,000,000,000,000). To put things in perspective, there areabout 1E23 (100,000,000,000,000,000,000,000) atoms of hydrogenand oxygen in a cubic centimeter (cm3) of water.An example of doping is implanting with B (boron) with adosage of between about 1E12 and 1E13 atoms/cm2, and an energyof about 40 to 80 keV to produce a doping level of between 1E17and 1E18 atoms/cm3. (“/cm3” may also be written “cm−3”)DRAMshort for dynamic random access memory. DRAM is a type ofrandom access memory that stores each bit of data in a separatecapacitor within an integrated circuit. Since real capacitors leakcharge, the information eventually fades unless the capacitor chargeis refreshed periodically. Because of this refresh requirement, it is adynamic memory as opposed to SRAM and other static memory. Itsadvantage over SRAM is its structural simplicity: only onetransistor and a capacitor are required per bit, compared to sixtransistors in SRAM. This allows DRAM to reach very highdensity. Like SRAM, it is in the class of volatile memory devices,since it loses its data when the power supply is removed.eDRAMshort for embedded DRAM. eDRAM is a capacitor-based dynamicrandom access memory usually integrated on the same die or in thesame package as the main ASIC or processor, as opposed to externalDRAM modules and transistor-based SRAM typically used forcaches.etchingetching generally refers to the removal of material from a substrate(or structures formed on the substrate), and is often performed witha mask in place so that material may selectively be removed fromcertain areas of the substrate, while leaving the material unaffected,in other areas of the substrate. There are generally two categories ofetching, (i) wet etch and (ii) dry etch.Wet etch is performed with a solvent (such as an acid)which may be chosen for its ability to selectively dissolve a givenmaterial (such as oxide), while leaving another material (such aspolysilicon) relatively intact. This ability to selectively etch givenmaterials is fundamental to many semiconductor fabricationprocesses. A wet etch will generally etch a homogeneous material(e.g., oxide) isotropically, but a wet etch may also etchsingle-crystal materials (e.g. silicon wafers) anisotropically.Dry etch may be performed using a plasma. Plasmasystems can operate in several modes by adjusting the parameters ofthe plasma. Ordinary plasma etching produces energetic freeradicals, neutrally charged, that react at the surface of the wafer.Since neutral particles attack the wafer from all angles, this processis isotropic. Ion milling, or sputter etching, bombards the waferwith energetic ions of noble gases which approach the waferapproximately from one direction, and therefore this process ishighly anisotropic. Reactive-ion etching (RIE) operates underconditions intermediate between sputter and plasma etching andmay be used to produce deep, narrow features, such as STI trenches.FETshort for field effect transistor. The FET is a transistor that relies onan electric field to control the shape and hence the conductivity ofa “channel” in a semiconductor material. FETs are sometimes usedas voltage-controlled resistors. The terminals of FETs aredesignated source (S), drain (D) and gate (G).isotropicliterally, identical in all directions. An example of an isotropicprocess is dissolving a tablet in water. All exposed surfaces of thetablet are uniformly acted upon. (see “anisotropic”)lithographyIn lithography (or “photolithography”), a radiation sensitive “resist”coating is formed over one or more layers which are to be treated insome manner, such as to be selectively doped and/or to have apattern transferred thereto. The resist, which is sometimes referredto as a photoresist, is itself first patterned by exposing it to radiation,where the radiation (selectively) passes through an interveningmask or template containing the pattern. As a result, the exposed orunexposed areas of the resist coating become more or less soluble,depending on the type of photoresist used. A developer is then usedto remove the more soluble areas of the resist leaving a patternedresist. The pattered resist can then serve as a mask for theunderlying layers which can then be selectively treated, such as toreceive dopants and/or to undergo etching, for example.maskThe term “mask” may be given to a layer of material which isapplied over an underlying layer of material, and patterned to haveopenings, so that the underlying layer can be processed where thereare openings. After processing the underlying layer, the mask maybe removed. Common masking materials are photoresist (resist) andnitride. Nitride is usually considered to be a “hard mask”.metallizationMetallization refers to formation of metal contacts and interconnectsin the manufacturing of semiconductor devices. This generallyoccurs after the devices are completely formed, and ready to beconnected with one another. A first level or layer of metallization isusually referred to as “M1”.MOSshort for metal oxide semiconductor.MOSFETshort for metal oxide semiconductor field-effect transistor.MOSFET is by far the most common field-effect transistor in bothdigital and analog circuits. The MOSFET is composed of a channelof n-type or p-type semiconductor material, and is accordinglycalled an NMOSFET or a PMOSFET. (The ‘metal’ in the name is ananachronism from early chips where gates were metal; modernchips use polysilicon gates, but are still called MOSFETs).nitridecommonly used to refer to silicon nitride (chemical formula Si3N4).A dielectric material commonly used in integrated circuitmanufacturing. Forms an excellent mask (barrier) against oxidationof silicon (Si). Nitride is commonly used as a hard mask (HM).n-typesemiconductor in which concentration of electrons is higher than theconcentration of “holes”. See p-type.oxidecommonly used to refer to silicon dioxide (SiO2). Also known assilica. SiO2 is the most common insulator in semiconductor devicetechnology, particularly in silicon MOS/CMOS where it is used asa gate dielectric (gate oxide); high quality films are obtained bythermal oxidation of silicon. Thermal SiO2 forms a smooth,low-defect interface with Si, and can be also readily deposited byCVD. Oxide may also be used to fill STI trenches, form spacerstructures, and as an inter-level dielectric, for example.plasma etchingPlasma etching refers to dry etching in which semiconductor waferis immersed in plasma containing etching species; chemical etchingreaction is taking place at the same rate in any direction, i.e. etchingis isotropic; can be very selective; used in those applications inwhich directionality (anisotropy) of etching in not required, e.g. inresist stripping.polyshort for polycrystalline silicon (Si). Heavily doped poly Si iscommonly used as a gate contact in silicon MOS and CMOSdevices.p-typesemiconductor in which concentration of “holes” is higher than theconcentration of electrons. See n-type. Examples of p-type siliconinclude silicon doped (enhanced) with boron (B), Indium (In) andthe like.resistshort for photoresist. also abbreviated “PR”. Photoresist is oftenused as a masking material in photolithographic processes toreproduce either a positive or a negative image on a structure, priorto etching (removal of material which is not masked). PR is usuallywashed off after having served its purpose as a masking material.RIEshort for Reactive Ion Etching. RIE is a variation of plasma etchingin which during etching, the semiconductor wafer is placed on anRF powered electrode. The plasma is generated under low pressure(vacuum) by an electromagnetic field. It uses chemically reactiveplasma to remove material deposited on wafers. High-energy ionsfrom the plasma attack the wafer surface and react with it. The wafertakes on potential which accelerates etching species extracted fromplasma toward the etched surface. A chemical etching reaction ispreferentially taking place in the direction normal to the surface - inother words, etching is more anisotropic than in plasma etching butis less selective. RIE typically leaves the etched surface damaged.RIE is the most common etching mode in semiconductormanufacturing.SiSilicon, a semiconductor.SOIshort for silicon-on-insulator. Silicon on insulator (SOI) technologyrefers to the use of a layered silicon-insulator-silicon substrate inplace of a conventional silicon substrate in semiconductormanufacturing, especially microelectronics. SOI-based devicesdiffer from conventional silicon-built devices in that the siliconjunction is above an electrical insulator, typically silicon dioxide or(less commonly) sapphire.STIshort for shallow trench isolation. Generally, a trench etched intothe substrate and filled with an insulating material such as oxide, toisolate one region of the substrate from an adjacent region of thesubstrate. One or more transistors of a given polarity may bedisposed within an area isolated by STI.substratetypically a wafer, of semiconductor material such as silicon,germanium, silicon germanium, silicon carbide, and thoseconsisting essentially of III-V compound semiconductors such asGaAs, II-VI compound semiconductors such as ZnSe. A substratemay also comprise an organic semiconductor or a layeredsemiconductor such as, for example, Si/SiGe, a silicon-on-insulatoror a SiGe-on-insulator. A portion or entire semiconductor substratemay be amorphous, polycrystalline, or monocrystalline. In additionto the aforementioned types of semiconductor substrates, thesemiconductor substrate employed in the present invention mayalso comprise a hybrid oriented (HOT) semiconductor substrate inwhich the HOT substrate has surface regions of differentcrystallographic orientation. The semiconductor substrate may bedoped, undoped or contain doped regions and undoped regionstherein. The semiconductor substrate may contain regions with orwithout strain therein, or contain regions of tensile strain andcompressive strain. A substrate is often covered by an oxide layer(sometimes referred to as a “pad oxide layer”). Pad oxide is usuallyrelatively thin, e.g., in the range of about 50 to about 500 Angstroms(5-50 nm), and can be formed, for example, by thermal oxidation ofthe substrate. Pad oxide may also be prepared by other methods. Forexample, silicon dioxide or reactive precursors like silane could bedeposited by chemical vapor deposition (CVD). A nitride layer(sometimes referred to as a “pad nitride layer”) may be formed toprotect the pad oxide and the underlying substrate during variousprocessing steps. It usually has a thickness in the range of about 100Angstroms to about 6000 Angstroms (10-600 nm), such as in therange of about 1500 Angstroms to about 3000 Angstroms(150-300 nm). Conventional means can be used to apply the padnitride, such as chemical vapor deposition (CVD).TransistorA transistor is a semiconductor device, commonly used as anamplifier or an electrically controlled switch. The transistor is thefundamental building block of the circuitry in computers, cellularphones, and all other modern electronic devices. Because of its fastresponse and accuracy, the transistor is used in a wide variety ofdigital and analog functions, including amplification, switching,voltage regulation, signal modulation, and oscillators. Transistorsmay be packaged individually or as part of an integrated circuit,some with over a billion transistors in a very small area. See FETUnits of LengthVarious units of length may be used herein, as follows:meter (m)A meter is the SI unit of length, slightly longer than a yard.1 meter = ~39 inches. 1 kilometer(km) = 1000 meters = ~0.6 miles.1,000,000 microns = 1 meter. 1,000 millimeters (mm) = 1meter.100 centimeters (cm) = 1 meter.micron (μm)one millionth of a meter (0.000001 meter); also referred toas a micrometer.mil1/1000 or 0.001 of an inch; 1 mil = 25.4 microns.nanometer (nm)one billionth of a meter (0.000000001 meter).Angstrom ({acute over (Å)})one tenth of a billionth of a meter. 10 {acute over (Å)} = 1 nm.Vshort for voltage. Different voltages may be applied to differentparts of a transistor or memory cell to control its operation, such as:Vbshort for bulk (or substrate) voltageVdshort for drain voltageVgshort for gate voltageVnshort for node voltageVplshort for plate voltageVsshort for source voltageVtshort for threshold voltageSee also KeVwaferIn microelectronics, a wafer is a thin slice of semiconductingmaterial, such as a silicon crystal, upon which microcircuits areconstructed. There are multiple orientation planes in the siliconcrystal that can be used. The planes are defined by the “MillerIndices” methodology. Common orientations classified by the“Miller indices” are (100), (011), (110), and (111).